The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device having copper interconnects. The present invention has particular applicability to high density semiconductor devices with submicron design features.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional methodology.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and multiple dielectric and conductive layers formed thereon. In a conventional semiconductor device 100 illustrated in FIG. 1, substrate 1 is provided with field oxide 2 for isolating an active region including source/drain regions 3, and a gate electrode 4, typically of doped polysilicon, above the semiconductor substrate with gate oxide 5 therebetween. Interlayer dielectric layer 6, typically silicon dioxide, is then deposited thereover and openings formed using conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer 8 and source/drain regions 3 through contacts 7, and to transistor gate electrode 49. Dielectric layer 9, typically silicon dioxide, is deposited on conductive layer 8, and another conductive layer 10, typically aluminum or an aluminum-base alloy, is formed on dielectric layer 9 and electrically connected to conductive layer 8 through vias 11.
With continued reference to FIG. 1, conductive layer 10 is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer 12, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer 13 is deposited thereon. Protective dielectric layer 13 typically includes a nitride layer, such as silicon nitride (Si3N4). Alternatively, protective dielectric layer 13 may include a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer 13 provides scratch protection to the semiconductor device 100 and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer 13, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer 10 for external connection via bonding pad 14 and electrically conductive wires 15 or an external connection electrode (not shown).
Although only two conductive layers 8 and 10 are depicted in FIG. 1 for illustrative convenience, conventional semiconductor devices may include more than two conductive layers, e.g., five conductive metal layers, depending on design requirements. Also in the interest of illustrative convenience, FIG. 1 does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continue to shrink in size, the interconnect structures, such as contacts 7 and vias 11 enable the semiconductor device 100 to offer more packing density, higher speeds and more flexibility in circuit design. Various metals, such as aluminum and aluminum-base alloys, have typically been used to form the electrical interconnects. More recently, copper and copper-base alloys have also been used to fill the openings to form the electrical interconnects. In such cases, the copper is typically deposited via a single electroplating process. That is, a single plating solution employing one type of plating chemistry is supplied to an electroplating chamber where the electroplating proceeds to fill the openings that form the interconnects. One problem with copper interconnects is that copper has low electromigration resistance and readily diffuses through silicon dioxide, the typical dielectric interlayer used in the manufacture of semiconductor devices.
In some prior processes, a dopant has been added to the copper to enhance the low electromigration resistance of copper. The dopant element forms intermetallic compounds with the copper and increases the electromigration resistance of the copper. In processes that employ copper alloys, however, the copper alloy is typically deposited throughout the entire opening that will form the interconnect or deposited and annealed to diffuse the dopant element throughout the entire interconnect structure. This use of copper alloys may help solve electromigration problems, but including the dopant throughout the entire interconnect increases the resistivity of the interconnect. This increased resistivity leads to slower processing associated with the semiconductor device.
There exists a need for a semiconductor device and a method for manufacturing a semiconductor device that improves electromigration problems associated with copper interconnects while maintaining low resistivity of the interconnect.
These and other needs are met by the present invention, where substantially pure copper is introduced into the lower portion of an interconnect opening followed by the introduction of doped copper at the top portion of the opening. The copper interconnect is then planarized, resulting in a copper interconnect having reduced electromigration and low overall resistivity.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming an interconnect in a semiconductor device. The method includes forming an opening in a dielectric layer and depositing substantially pure copper to fill a portion of the opening. The method also includes depositing doped copper over the substantially pure copper to fill the opening and planarizing the semiconductor device so that the filled opening is substantially coplanar with an upper surface of the dielectric layer.
According to another aspect of the invention, a semiconductor device is provided. The semiconductor device comprises a semiconductor substrate and a plurality of levels of dielectric layers and conductive layers formed on the semiconductor substrate. The semiconductor device also includes an interconnect formed in at least one of the dielectric layers. The interconnect electrically connects at least two of the conductive layers or one of the conductive layers and an active region in the semiconductor substrate. The interconnect includes a lower portion comprising substantially pure copper and an upper portion comprising doped copper.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.